TSMC admits it can't produce enough AI chips as demand outpaces supply

In context: Chip-on-wafer-on-substrate is a packaging technology that integrates multiple chips into a single package to create high-performance computing and AI components. The field is currently dominated by TSMC, though other Taiwanese firms such as UMC, ASE Technology Holding, and Powertech Technology are also entering the market.

With AI showing no signs of slowing, TSMC will be ramping up its advanced chip packaging capabilities over the next few years. During its recent earnings call on October 17, the chipmaker revealed that its production capacity for CoWoS packaging technology is set to double year-over-year in both 2024 and 2025.

However, demand is so strong that even with this rapid expansion, the company suggests it still can't produce packages fast enough for its customers.

Currently, advanced packaging accounts for only about seven to nine percent of TSMC's total revenue, but it is a fast-growing segment that is expected to outpace the company's overall growth over the next five years. While gross margins are slightly lower than TSMC's average, they are steadily improving as production volume increases.

Originally, the industry rumor mill expected TSMC's CoWoS capacity expansion to start leveling off by 2026. Early projections had the company's monthly packaging volume topping out around 100,000 to 120,000 wafers that year. But, surprise – AI's demand keeps growing.

With major AI players relentlessly driving demand for cutting-edge chips with advanced packaging, TSMC has returned to its equipment suppliers to plan for even greater CoWoS capacity in 2026, according to the report.

These suppliers likely include companies like GPTC and Scientech, key providers of wet process equipment, such as automated wet benches and single wafer spin processors, which TSMC relies on. Scientech, in particular, appears to have a strong grip on CoWoS equipment orders at the moment.

These suppliers could soon be printing cash as the report suggests TSMC could reach an astonishing 140,000 to 150,000 packaged wafers per month by 2026.

To put that in perspective, by the end of this year, the company expects its CoWoS capacity to reach around 35,000 to 40,000 wafers per month. In 2025, that figure is expected to surge to roughly 80,000 wafers.

Beyond ramping up production, the chipmaker reportedly plans to switch from conventional round wafers to rectangular substrates to increase the number of chips that can be placed on each wafer.