Huawei's Tau Scaling Law Redefines Chip Progress, Sidesteps US Sanctions

Huawei has unveiled a new chip design methodology that sidesteps US sanctions by focusing on signal speed rather than transistor shrinkage.

At the IEEE International Symposium on Circuits and Systems in Shanghai on May 25, He Tingbo, president of Huawei's semiconductor division, introduced the Tau Scaling Law. The approach moves away from traditional geometric scaling requiring ASML's EUV lithography tools. Instead, it optimizes data flow latency at the system level.

The technical core is a new 3D architecture called LogicFolding. Huawei projects it can achieve transistor density equivalent to 1.4 nm processes by 2031, with up to 55% better density and 41% improved power efficiency over current designs.

Huawei claims it has already mass-produced 381 chips using the new design principles over the past six years. The first Kirin smartphone chips built on LogicFolding are expected later in 2026.

Huawei's Ascend AI chips are already competing with Nvidia in China. If the Tau Scaling Law delivers, Huawei's competitive position will strengthen significantly, potentially capturing more domestic market share as Chinese firms face restrictions on buying Nvidia's most advanced products.

For investors, real-world performance from the upcoming Kirin chips will be critical. Successful commercial application could force the entire semiconductor industry to rethink progress metrics. However, projections about 2031 remain speculative, and yields on novel 3D architectures pose manufacturing risks.