A senior executive at TSMC, the world's largest contract chipmaker, said surging electricity demands from artificial intelligence are forcing a fundamental shift in semiconductor design. Kevin Zhang, TSMC's Senior Vice President of Business Development, told reporters in Amsterdam that energy efficiency, not just raw computing power, is now the primary constraint shaping future chips.
"The area customers most want improvement in is energy efficiency. This is true across the board, whether you are the edge guy, smartphone, mobile, IoT application, or high-performance AI data center," Zhang said.
The shift marks a turning point for the semiconductor industry. Simply packing more transistors onto chips is no longer enough to sustain performance gains for energy-hungry AI workloads. TSMC, which makes AI chips for Nvidia, AMD, Google, Amazon, Meta, and Microsoft, is now prioritizing approaches like advanced packaging, chip stacking, and photonics to boost efficiency.
Zhang said TSMC expects its chips to cut power consumption by up to 30 percent between its current N2 technology and its A14 generation, due around 2028, while delivering more than 20 percent higher computing performance.
The comments come as rivals explore alternative paths. Chinese competitor Huawei recently unveiled its 'Tau Scaling Law' plan to improve performance by speeding up data movement within chips, though it faces U.S.-led export controls blocking access to advanced Dutch ASML lithography machines.
TSMC, a major buyer of ASML's EUV systems, said in April it would delay adoption of next-generation lithography technology, highlighting how energy efficiency improvements are becoming more urgent than smaller circuitry for the coming generation of AI chips.