IBM has unveiled a chip design breakthrough that pushes transistor density into the sub-1 nanometer scale. The NanoStack architecture packs nearly 100 billion transistors onto a surface the size of a fingernail-roughly equivalent to a 0.7nm process, making it the first known chip technology below 1nm.
In prototype tests, the new chip delivered a 50% performance improvement and 70% greater energy efficiency compared to IBM’s own 2nm chip. Jay Gambetta, director of IBM Research, called the achievement a 'landmark moment,' emphasizing that the 3D stacking approach reimagines how chips are built.
The method layers sheets of transistors vertically in a 'skyscraper' configuration, stretching Moore’s Law further. Professor Alan Woodward of Surrey University likened it to a 100-story building, while rival 3D designs from Samsung and Intel are closer to 30-50 stories. Heat dissipation and switching reliability remain key hurdles, and commercial production is still years away.