IBM Research has announced a new chip architecture, nanostack, which vertically stacks transistors to pack nearly 100 billion transistors on a chip the size of a fingernail. The “sub-1 nanometer” technology, designated a 7-angstrom node, does not physically shrink features below 1nm but delivers a corresponding performance leap.
The basic building block bonds two transistors, each with three nanosheets 5nm thick and separated by 9nm. IBM projects a 50% increase in computing performance or a 70% reduction in energy use compared to its previous 2nm node.
For AI workloads, a staggered-channel design yields a 40% improvement in SRAM scaling, reducing memory cell height by 40% and enabling more SRAM per chip. IBM’s nanosheet transistors already underpin the industry’s 3nm and 2nm nodes through partnerships and independent adoption by foundries like TSMC.
IBM expects nanostack technology to reach commercial manufacturing within five to ten years, ultimately replacing nanosheets for CPUs and GPUs.